A low-latency, low-area hardware oblivious RAM controller

C.W. Fletcher; L. Ren; A. Kwon; M. Van Dijk; E. Stefanov; D. Serpanos; S. Devadas

doi:10.1109/FCCM.2015.58

A low-latency, low-area hardware oblivious RAM controller

C.W. Fletcher
, L. Ren
, A. Kwon
, M. Van Dijk
, E. Stefanov
, D. Serpanos
, S. Devadas

Research output: Chapter in Book / Report / Conference proceeding › Conference contribution › Academic › peer-review

Abstract

© 2015 IEEE.We build and evaluate Tiny ORAM, an Oblivious RAM prototype on FPGA. Oblivious RAM is a cryptographic primitive that completely obfuscates an application's data, access pattern, and read/write behavior to/from external memory (such as DRAM or disk). Tiny ORAM makes two main contributions. First, by removing an algorithmic bottleneck in prior work, Tiny ORAM is the' first hardware ORAM design to support arbitrary block sizes (e.g., 64 Bytes to 4096 Bytes). With a 64 Byte block size, Tiny ORAM can ' finish an access in 1:4us, over 40x faster than the prior-art implementation. Second, through novel algorithmic and engineering-level optimizations, Tiny ORAM reduces the number of symmetric encryption operations by 3x compared to a prior work. Tiny ORAM is also the ' first design to implement and report real numbers for the cost of symmetric encryption in hardware ORAM constructions. Putting it together, Tiny ORAM requires 18381 (5%) LUTs and 146 (13%) Block RAM on a Xilinx XC7VX485T FPGA, including the cost of encryption.

Original language	English
Title of host publication	Proceedings - 2015 IEEE 23rd Annual International Symposium on Field-Programmable Custom Computing Machines, FCCM 2015
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	215-222
ISBN (Electronic)	9781479999699
DOIs	https://doi.org/10.1109/FCCM.2015.58
Publication status	Published - 15 Jul 2015
Externally published	Yes
Event	23rd IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, FCCM 2015 - Vancouver, Canada Duration: 3 May 2015 → 5 May 2015

Conference

Conference	23rd IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, FCCM 2015
Country/Territory	Canada
City	Vancouver
Period	3/05/15 → 5/05/15

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

SDG 7 Affordable and Clean Energy

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10.1109/FCCM.2015.58

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Fletcher, C. W., Ren, L., Kwon, A., Van Dijk, M., Stefanov, E., Serpanos, D., & Devadas, S. (2015). A low-latency, low-area hardware oblivious RAM controller. In Proceedings - 2015 IEEE 23rd Annual International Symposium on Field-Programmable Custom Computing Machines, FCCM 2015 (pp. 215-222). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/FCCM.2015.58

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title = "A low-latency, low-area hardware oblivious RAM controller",

abstract = "{\textcopyright} 2015 IEEE.We build and evaluate Tiny ORAM, an Oblivious RAM prototype on FPGA. Oblivious RAM is a cryptographic primitive that completely obfuscates an application's data, access pattern, and read/write behavior to/from external memory (such as DRAM or disk). Tiny ORAM makes two main contributions. First, by removing an algorithmic bottleneck in prior work, Tiny ORAM is the' first hardware ORAM design to support arbitrary block sizes (e.g., 64 Bytes to 4096 Bytes). With a 64 Byte block size, Tiny ORAM can ' finish an access in 1:4us, over 40x faster than the prior-art implementation. Second, through novel algorithmic and engineering-level optimizations, Tiny ORAM reduces the number of symmetric encryption operations by 3x compared to a prior work. Tiny ORAM is also the ' first design to implement and report real numbers for the cost of symmetric encryption in hardware ORAM constructions. Putting it together, Tiny ORAM requires 18381 (5\%) LUTs and 146 (13\%) Block RAM on a Xilinx XC7VX485T FPGA, including the cost of encryption.",

author = "C.W. Fletcher and L. Ren and A. Kwon and \{Van Dijk\}, M. and E. Stefanov and D. Serpanos and S. Devadas",

year = "2015",

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doi = "10.1109/FCCM.2015.58",

language = "English",

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booktitle = "Proceedings - 2015 IEEE 23rd Annual International Symposium on Field-Programmable Custom Computing Machines, FCCM 2015",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

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note = "23rd IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, FCCM 2015 ; Conference date: 03-05-2015 Through 05-05-2015",

}

Fletcher, CW, Ren, L, Kwon, A, Van Dijk, M, Stefanov, E, Serpanos, D & Devadas, S 2015, A low-latency, low-area hardware oblivious RAM controller. in Proceedings - 2015 IEEE 23rd Annual International Symposium on Field-Programmable Custom Computing Machines, FCCM 2015. Institute of Electrical and Electronics Engineers Inc., pp. 215-222, 23rd IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, FCCM 2015, Vancouver, Canada, 3/05/15. https://doi.org/10.1109/FCCM.2015.58

A low-latency, low-area hardware oblivious RAM controller. / Fletcher, C.W.; Ren, L.; Kwon, A. et al.
Proceedings - 2015 IEEE 23rd Annual International Symposium on Field-Programmable Custom Computing Machines, FCCM 2015. Institute of Electrical and Electronics Engineers Inc., 2015. p. 215-222.

Research output: Chapter in Book / Report / Conference proceeding › Conference contribution › Academic › peer-review

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ER -

A low-latency, low-area hardware oblivious RAM controller

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