TY - GEN
T1 - Architecture-aware design and implementation of CNN algorithms for embedded inference
T2 - 30th International Conference on Microelectronics, ICM 2018
AU - Meloni, Paolo
AU - Loi, Daniela
AU - Deriu, Gianfranco
AU - Pimentel, Andy D.
AU - Saprat, Dolly
AU - Pintort, Maura
AU - Biggio, Battista
AU - Ripolles, Oscar
AU - Solans, David
AU - Conti, Francesco
AU - Benini, Luca
AU - Stefanov, Todor
AU - Minakova, Svetlana
AU - Moser, Bernhard
AU - Shepeleva, Natalia
AU - Masin, Michael
AU - Palumbo, Francesca
AU - Fragoulis, Nikos
AU - Theodorakopoulos, Ilias
PY - 2018/7/2
Y1 - 2018/7/2
N2 - The use of Deep Learning (DL) algorithms is increasingly evolving in many application domains. Despite the rapid growing of algorithm size and complexity, performing DL inference at the edge is becoming a clear trend to cope with low latency, privacy and bandwidth constraints. Nevertheless, traditional implementation on low-energy computing nodes often requires experience-based manual intervention and trial-and-error iterations to get to a functional and effective solution. This work presents a computer-aided design (CAD) support for effective implementation of DL algorithms on embedded systems, aiming at automating different design steps and reducing cost. The proposed tool flow comprises capabilities to consider architecture-and hardware-related variables at very early stages of the development process, from pre-training hyperparameter optimization and algorithm configuration to deployment, and to adequately address security, power efficiency and adaptivity requirements. This paper also presents some preliminary results obtained by the first implementation of the optimization techniques supported by the tool flow.
AB - The use of Deep Learning (DL) algorithms is increasingly evolving in many application domains. Despite the rapid growing of algorithm size and complexity, performing DL inference at the edge is becoming a clear trend to cope with low latency, privacy and bandwidth constraints. Nevertheless, traditional implementation on low-energy computing nodes often requires experience-based manual intervention and trial-and-error iterations to get to a functional and effective solution. This work presents a computer-aided design (CAD) support for effective implementation of DL algorithms on embedded systems, aiming at automating different design steps and reducing cost. The proposed tool flow comprises capabilities to consider architecture-and hardware-related variables at very early stages of the development process, from pre-training hyperparameter optimization and algorithm configuration to deployment, and to adequately address security, power efficiency and adaptivity requirements. This paper also presents some preliminary results obtained by the first implementation of the optimization techniques supported by the tool flow.
UR - http://www.scopus.com/inward/record.url?scp=85065719864&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=85065719864&partnerID=8YFLogxK
U2 - 10.1109/ICM.2018.8704093
DO - 10.1109/ICM.2018.8704093
M3 - Conference contribution
AN - SCOPUS:85065719864
T3 - Proceedings of the International Conference on Microelectronics, ICM
SP - 52
EP - 55
BT - Proceeding of 2018 30th International Conference on Microelectronics, ICM 2018
PB - Institute of Electrical and Electronics Engineers Inc.
Y2 - 16 December 2018 through 19 December 2018
ER -