TY - GEN
T1 - Caches and hash trees for efficient memory integrity verification
AU - Gassend, B.
AU - Suh, G.E.
AU - Clarke, D.
AU - Van Dijk, M.
AU - Devadas, S.
PY - 2003
Y1 - 2003
N2 - © 2003 IEEE.We study the hardware cost of implementing hash-tree based verification of untrusted external memory by a high performance processor. This verification could enable applications such as certified program execution. A number of schemes are presented with different levels of integration between the on-processor L2 cache and the hash-tree machinery. Simulations show that for the best of our methods, the performance overhead is less than 25%, a significant decrease from the 10× overhead of a naive implementation.
AB - © 2003 IEEE.We study the hardware cost of implementing hash-tree based verification of untrusted external memory by a high performance processor. This verification could enable applications such as certified program execution. A number of schemes are presented with different levels of integration between the on-processor L2 cache and the hash-tree machinery. Simulations show that for the best of our methods, the performance overhead is less than 25%, a significant decrease from the 10× overhead of a naive implementation.
UR - https://www.scopus.com/pages/publications/84955507265
UR - https://www.scopus.com/inward/citedby.url?scp=84955507265&partnerID=8YFLogxK
U2 - 10.1109/HPCA.2003.1183547
DO - 10.1109/HPCA.2003.1183547
M3 - Conference contribution
T3 - Proceedings - International Symposium on High-Performance Computer Architecture
SP - 295
EP - 306
BT - Proceedings - 9th International Symposium on High-Performance Computer Architecture, HPCA 2003
PB - IEEE Computer Society
T2 - 9th IEEE International Symposium on High-Performance Computer Architecture, HPCA 2003
Y2 - 8 February 2003 through 12 February 2003
ER -
