Abstract
Since the inception of computing, we have been reliant on CPU-powered architectures. However, today this reliance is challenged by manufacturing limitations (CMOS scaling), performance expectations (stalled clocks, Turing tax), and security concerns (microarchitectural attacks). To re-imagine our computing architecture, in this work, we take a more radical, but pragmatic approach and propose to eliminate the CPU with its design baggage from data center computing. We integrate three primary pillars of computing, i.e., networking, storage, and computing, into a single, self-hosting, unified CPU-free Data Processing Unit (DPU) called Hyperion. The elimination of the CPU from computing necessitates re-thinking our computing, networking, and storage abstractions, and tackle the associated challenges which we sketch in this paper. We share the blueprint of our work-in-progress, Hyperion's hardware and software stack, and seek feedback.
| Original language | English |
|---|---|
| Title of host publication | HotOS 2023 |
| Subtitle of host publication | Proceedings of the 19th Workshop on Hot Topics in Operating Systems |
| Publisher | Association for Computing Machinery, Inc |
| Pages | 1-14 |
| Number of pages | 14 |
| ISBN (Electronic) | 9798400701955 |
| DOIs | |
| Publication status | Published - Jun 2023 |
| Event | 19th Workshop on Hot Topics in Operating Systems, HotOS 2023 - Providence, United States Duration: 22 Jun 2023 → 24 Jun 2023 |
Conference
| Conference | 19th Workshop on Hot Topics in Operating Systems, HotOS 2023 |
|---|---|
| Country/Territory | United States |
| City | Providence |
| Period | 22/06/23 → 24/06/23 |
Bibliographical note
Funding Information:This work is supported by the Dutch Research Council (NWO) grants OCENW.XS3.030 and OCENW.KLEIN.561, and Xilinx University Donation Program. The authors thank Marco Bonola, Giulia Frascaria, Corne Lukken, Kaveh Razavi, Herbert Bos, Tiziano De Matteis, Ana-Lucia Varbanescu, Alexandru Iosup, and the HotOS’23 reviewers for their constructive feedback. We would like to express our special gratitude to Jonas Pfefferle (IBM Research) who presented this work on the behalf of the authors at HotOS’23.
Funding Information:
Inspired by the LLVM project, in this work, we argue that FPGA programming needs to decouple the frontend (application logic) and backend (HDL codes) with an accelerator-independent, intermediate representation (IR) language. The IR can be used to reason about correctness and safety properties of the program, with compiler-assisted transformations for pointer swizzling and privilege calls. We make a case that the extended Berkeley Packet Filter (eBPF) [42, 120] language is a suitable match for such an IR for three key reasons. First, eBPF is not tied to a specific application-domain and it is used in networking [7, 72], tracing [66], caching [62], security [88], and (very successfully) storage [21, 29, 101, 114, 173]. It is also supported by healthy, growing communities (Cilium, the eBPF foundation), thus establishing expertise and a knowledge base. Second, due to the simplified nature of the eBPF instruction set, it is possible to verify and reason about its execution. The Linux kernel already ships with an eBPF verifier [156] (with simplified symbolic execution checks). Lastly, eBPF supports efficiently generating codes for multiple hardware devices such as x86, ARM, or FPGAs, thus solidifying its position as an accelerator-independent unifying IR [90].
Publisher Copyright:
© 2023 Owner/Author(s).
Funding
This work is supported by the Dutch Research Council (NWO) grants OCENW.XS3.030 and OCENW.KLEIN.561, and Xilinx University Donation Program. The authors thank Marco Bonola, Giulia Frascaria, Corne Lukken, Kaveh Razavi, Herbert Bos, Tiziano De Matteis, Ana-Lucia Varbanescu, Alexandru Iosup, and the HotOS’23 reviewers for their constructive feedback. We would like to express our special gratitude to Jonas Pfefferle (IBM Research) who presented this work on the behalf of the authors at HotOS’23. Inspired by the LLVM project, in this work, we argue that FPGA programming needs to decouple the frontend (application logic) and backend (HDL codes) with an accelerator-independent, intermediate representation (IR) language. The IR can be used to reason about correctness and safety properties of the program, with compiler-assisted transformations for pointer swizzling and privilege calls. We make a case that the extended Berkeley Packet Filter (eBPF) [42, 120] language is a suitable match for such an IR for three key reasons. First, eBPF is not tied to a specific application-domain and it is used in networking [7, 72], tracing [66], caching [62], security [88], and (very successfully) storage [21, 29, 101, 114, 173]. It is also supported by healthy, growing communities (Cilium, the eBPF foundation), thus establishing expertise and a knowledge base. Second, due to the simplified nature of the eBPF instruction set, it is possible to verify and reason about its execution. The Linux kernel already ships with an eBPF verifier [156] (with simplified symbolic execution checks). Lastly, eBPF supports efficiently generating codes for multiple hardware devices such as x86, ARM, or FPGAs, thus solidifying its position as an accelerator-independent unifying IR [90].
Keywords
- accelerators
- CPU-free computing
- data processing
- data storage
- programming