TY - GEN
T1 - Efficient memory integrity verification and encryption for secure processors
AU - Suh, G.E.
AU - Clarke, D.
AU - Gasend, B.
AU - Van Dijk, M.
AU - Devadas, S.
PY - 2003
Y1 - 2003
N2 - © 2003 IEEE.Secure processors enable new sets of applications such as commercial grid computing, software copy-protection, and secure mobile agents by providing security from both physical and software attacks. This paper proposes new hardware mechanisms for memory integrity verification and encryption, which are two key primitives required in single-chip secure processors. The integrity verification mechanism offers significant performance advantages over existing ones when the checks are infrequent as in grid computing applications. The encryption mechanism improves the performance in all cases.
AB - © 2003 IEEE.Secure processors enable new sets of applications such as commercial grid computing, software copy-protection, and secure mobile agents by providing security from both physical and software attacks. This paper proposes new hardware mechanisms for memory integrity verification and encryption, which are two key primitives required in single-chip secure processors. The integrity verification mechanism offers significant performance advantages over existing ones when the checks are infrequent as in grid computing applications. The encryption mechanism improves the performance in all cases.
UR - https://www.scopus.com/pages/publications/84944412608
UR - https://www.scopus.com/inward/citedby.url?scp=84944412608&partnerID=8YFLogxK
U2 - 10.1109/MICRO.2003.1253207
DO - 10.1109/MICRO.2003.1253207
M3 - Conference contribution
T3 - Proceedings of the Annual International Symposium on Microarchitecture, MICRO
SP - 339
EP - 350
BT - Proceedings - 36th International Symposium on Microarchitecture, MICRO 2003
PB - IEEE Computer Society
T2 - 36th International Symposium on Microarchitecture, MICRO 2003
Y2 - 3 December 2003 through 5 December 2003
ER -
