Exploiting Lithography Limits for Hardware Security Applications

R.S. Khan; H. Silva; N. Noor; C. Jin; S. Muneer; F. Dirisaglik; A. Cywar; P.H. Nguyen; M. Van Dijk; A. Gokirmak

doi:10.1109/NANO46743.2019.8993902

Exploiting Lithography Limits for Hardware Security Applications

R.S. Khan, H. Silva, N. Noor, C. Jin, S. Muneer, F. Dirisaglik, A. Cywar, P.H. Nguyen, M. Van Dijk, A. Gokirmak

Research output: Chapter in Book / Report / Conference proceeding › Conference contribution › Academic › peer-review

Abstract

© 2019 IEEE.Hardware security primitives such as physical obfuscated keys (POKs) allow tamper-resistant storage of random keys based on manufacturing or physical variability. The output bits of existing POK designs need to be first corrected due to measurement noise using error correction methods and then de-correlated by privacy amplification processes. These additional requirements increase the hardware overhead and reduce the efficiency of the system. In this work, we propose an intrinsically reliable POK design capable of generating random bits by exploiting the limits of the lithographic process for a given technology. Our design does not require any error correction and requires only XOR circuits for privacy amplification which reduces the hardware overhead of the whole system.

Original language	English
Title of host publication	19th IEEE International Conference on Nanotechnology, NANO 2019
Publisher	IEEE Computer Society
Pages	9-12
ISBN (Electronic)	9781728128917
DOIs	https://doi.org/10.1109/NANO46743.2019.8993902
Publication status	Published - 1 Jul 2019
Externally published	Yes
Event	19th IEEE International Conference on Nanotechnology, NANO 2019 - Macau, China Duration: 22 Jul 2019 → 26 Jul 2019

Publication series

Name	Proceedings of the IEEE Conference on Nanotechnology
ISSN (Print)	1944-9399
ISSN (Electronic)	1944-9380

Conference

Conference	19th IEEE International Conference on Nanotechnology, NANO 2019
Country/Territory	China
City	Macau
Period	22/07/19 → 26/07/19

Funding

*This research is supported by the multi-university research initiative (MURI) of Air Force Office of Scientific Research (AFOSR) under the grant FA9550-14-1-0351Z.

Funders	Funder number
National Science Foundation	1711626
Air Force Office of Scientific Research	FA9550-14-1-0351Z

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

Access to Document

10.1109/NANO46743.2019.8993902

Persistent URL (handle)

Copy link address

Cite this

Khan, R. S., Silva, H., Noor, N., Jin, C., Muneer, S., Dirisaglik, F., Cywar, A., Nguyen, P. H., Van Dijk, M., & Gokirmak, A. (2019). Exploiting Lithography Limits for Hardware Security Applications. In 19th IEEE International Conference on Nanotechnology, NANO 2019 (pp. 9-12). Article 8993902 (Proceedings of the IEEE Conference on Nanotechnology). IEEE Computer Society. https://doi.org/10.1109/NANO46743.2019.8993902

@inproceedings{b53dc10ed3bb4238889b399921c4adfc,

title = "Exploiting Lithography Limits for Hardware Security Applications",

abstract = "{\textcopyright} 2019 IEEE.Hardware security primitives such as physical obfuscated keys (POKs) allow tamper-resistant storage of random keys based on manufacturing or physical variability. The output bits of existing POK designs need to be first corrected due to measurement noise using error correction methods and then de-correlated by privacy amplification processes. These additional requirements increase the hardware overhead and reduce the efficiency of the system. In this work, we propose an intrinsically reliable POK design capable of generating random bits by exploiting the limits of the lithographic process for a given technology. Our design does not require any error correction and requires only XOR circuits for privacy amplification which reduces the hardware overhead of the whole system.",

author = "R.S. Khan and H. Silva and N. Noor and C. Jin and S. Muneer and F. Dirisaglik and A. Cywar and P.H. Nguyen and {Van Dijk}, M. and A. Gokirmak",

year = "2019",

month = jul,

day = "1",

doi = "10.1109/NANO46743.2019.8993902",

language = "English",

series = "Proceedings of the IEEE Conference on Nanotechnology",

publisher = "IEEE Computer Society",

pages = "9--12",

booktitle = "19th IEEE International Conference on Nanotechnology, NANO 2019",

note = "19th IEEE International Conference on Nanotechnology, NANO 2019 ; Conference date: 22-07-2019 Through 26-07-2019",

}

Khan, RS, Silva, H, Noor, N, Jin, C, Muneer, S, Dirisaglik, F, Cywar, A, Nguyen, PH, Van Dijk, M & Gokirmak, A 2019, Exploiting Lithography Limits for Hardware Security Applications. in 19th IEEE International Conference on Nanotechnology, NANO 2019., 8993902, Proceedings of the IEEE Conference on Nanotechnology, IEEE Computer Society, pp. 9-12, 19th IEEE International Conference on Nanotechnology, NANO 2019, Macau, China, 22/07/19. https://doi.org/10.1109/NANO46743.2019.8993902

Exploiting Lithography Limits for Hardware Security Applications. / Khan, R.S.; Silva, H.; Noor, N. et al.
19th IEEE International Conference on Nanotechnology, NANO 2019. IEEE Computer Society, 2019. p. 9-12 8993902 (Proceedings of the IEEE Conference on Nanotechnology).

Research output: Chapter in Book / Report / Conference proceeding › Conference contribution › Academic › peer-review

TY - GEN

T1 - Exploiting Lithography Limits for Hardware Security Applications

AU - Khan, R.S.

AU - Silva, H.

AU - Noor, N.

AU - Jin, C.

AU - Muneer, S.

AU - Dirisaglik, F.

AU - Cywar, A.

AU - Nguyen, P.H.

AU - Van Dijk, M.

AU - Gokirmak, A.

PY - 2019/7/1

Y1 - 2019/7/1

N2 - © 2019 IEEE.Hardware security primitives such as physical obfuscated keys (POKs) allow tamper-resistant storage of random keys based on manufacturing or physical variability. The output bits of existing POK designs need to be first corrected due to measurement noise using error correction methods and then de-correlated by privacy amplification processes. These additional requirements increase the hardware overhead and reduce the efficiency of the system. In this work, we propose an intrinsically reliable POK design capable of generating random bits by exploiting the limits of the lithographic process for a given technology. Our design does not require any error correction and requires only XOR circuits for privacy amplification which reduces the hardware overhead of the whole system.

AB - © 2019 IEEE.Hardware security primitives such as physical obfuscated keys (POKs) allow tamper-resistant storage of random keys based on manufacturing or physical variability. The output bits of existing POK designs need to be first corrected due to measurement noise using error correction methods and then de-correlated by privacy amplification processes. These additional requirements increase the hardware overhead and reduce the efficiency of the system. In this work, we propose an intrinsically reliable POK design capable of generating random bits by exploiting the limits of the lithographic process for a given technology. Our design does not require any error correction and requires only XOR circuits for privacy amplification which reduces the hardware overhead of the whole system.

UR - http://www.scopus.com/inward/record.url?scp=85081048930&partnerID=8YFLogxK

U2 - 10.1109/NANO46743.2019.8993902

DO - 10.1109/NANO46743.2019.8993902

M3 - Conference contribution

T3 - Proceedings of the IEEE Conference on Nanotechnology

SP - 9

EP - 12

BT - 19th IEEE International Conference on Nanotechnology, NANO 2019

PB - IEEE Computer Society

T2 - 19th IEEE International Conference on Nanotechnology, NANO 2019

Y2 - 22 July 2019 through 26 July 2019

ER -

Exploiting Lithography Limits for Hardware Security Applications

Abstract

Publication series

Conference

Funding

UN SDGs

Access to Document

Persistent URL (handle)

Other files and links

Fingerprint

Cite this