Phase I Upgrade of the Readout System of the Vertex Detector at the LHCb Experiment

Antonio Fernandez Prieto, Pablo Vazquez Regueiro, Karol Hennessy, Jan Buytaert, Martin Van Beuzekom, Edgar Lemos Cid, Lars Eklund, Kristof De Bruyn, Sneha Naik, Manuel Schiller, Donal Murray, Alexander Leflat, Oscar Boente Garcia, Abraham Gallas Torreira, Beatriz Garcia Plana, Themis Bowcock, Francesco Dettori, Karlis Dreimanis, Vinicius Franco Lima, David HutchcroftKurt Rinnert, Tara Shears, Oscar Augusto, Victor Coco, Paula Collins, Tim Evans, Massi Ferro-Luzzi, Wolfgang Funk, Heinrich Schindler, Kazu Akiba, Elena Dall'occo, Cristina Sanchez Graz, Wouter Hulsbergen, Daniel Hynds, Igor Kostiuk, Marcel Merk, Aleksandra Snoch, Dana Seman Bobulska, Silvia Borghi, Stefano De Capua, Deepanwita Dutta, Marco Gersabeck, Chris Parkes, Peter Svihra, Mark Williams, Galina Bogdanova, Vladimir Volkov, Pawel Kopciewicz, MacIej Majewski, Agnieszka Oblakowska-Mucha, Bartlomej Rachwal, Tomasz Szumlak, Lucas Meyer Garcia, Franciole Marinho, Larissa Helena Mendes, Irina Nasteva, Juan Otalora, Gabriel Rodrigues, Jaap Velthuis, Pawel Jalocha, Malcolm John, Nathan Jurik, Luke Scantlebury-Smead, John Back, Tim Gershon, Tom Latham, Andrew Morris

Research output: Contribution to JournalArticleAcademicpeer-review

Abstract

This article describes the high-speed system designed to meet the challenging requirements for the readout of the new pixel VErtex LOcator (VELO) of the upgraded LHCb experiment. All elements of the electronics readout chain will be renewed to cope with the requirement of 40-MHz full-event readout rate. The pixel sensors will be equipped with VeloPix ASICs and placed at 5 mm from the Large Hadron Collider (LHC) beams in a secondary vacuum tank in an extremely high and nonhomogeneous radiation environment. The front-end (FE) ASICs with the highest occupancy will have to cope with pixel-hit rates above 900 Mhits/s using up to four 5.13-Gb/s data readout links. Each module comprises six VeloPix ASICs, wire-bonded to two FE hybrid boards, while a third hybrid will employ a GBTx ASIC as the control interface. High-speed data will reach the wall of the vacuum chamber through low-mass flexible copper tapes. A custom board routes the signals outside the vacuum tank. On the air side, an optical and power board converts the electrical high-speed signals into optical signals for transmission from the underground cavern to the off-detector electronics that process data and send them to a farm of computers for further analysis. Several tests allowing the validation of the system are described here with special emphasis on a test with proton beams that confirms the correct operation of the whole readout hardware.
Original languageEnglish
Article number8976212
Pages (from-to)732-739
JournalIEEE Transactions on Nuclear Science
Volume67
Issue number4
DOIs
Publication statusPublished - 1 Apr 2020
Externally publishedYes

Funding

Manuscript received October 25, 2019; revised December 18, 2019 and January 16, 2020; accepted January 24, 2020. Date of publication January 30, 2020; date of current version April 16, 2020. This work was supported in part by the Spanish Government, Ministry of Science, Innovation and Universities, in part by the Ministry of Economy and Competitiveness under the Unit of Excellence María de Maeztu, and in part by the Regional Government of Galicia, IGFAE Research Center and University of Santiago de Compostela.

FundersFunder number
Ministerio de Ciencia, Innovación y Universidades
Ministerio de Economía y Competitividad
Xunta de Galicia

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