Abstract
Recent rapid strides in memory safety tools and hardware have improved software quality and security. While coarse-grained memory safety has improved, achieving memory safety at the granularity of individual objects remains a challenge due to high performance overheads usually between ~1.7x-2.2x. In this paper, we present a novel idea called Califorms, and associated program observations, to obtain a low overhead security solution for practical, byte-granular memory safety. The idea we build on is called memory blacklisting, which prohibits a program from accessing certain memory regions based on program semantics. State of the art hardware-supported memory blacklisting, while much faster than software blacklisting, creates memory fragmentation (on the order of few bytes) for each use of the blacklisted location. We observe that metadata used for blacklisting can be stored in dead spaces in a program's data memory and that this metadata can be integrated into the microarchitecture by changing the cache line format. Using these observations, a Califorms based system proposed in this paper reduces the performance overheads of memory safety to ~1.02x-1.16x while providing bytegranular protection and maintaining very low hardware overheads. Moreover, the fundamental idea of storingmetadata in empty spaces and changing cache line formats can be used for other security and performance applications.
| Original language | English |
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| Title of host publication | MICRO 2019 |
| Subtitle of host publication | Proceedings of the 52nd Annual IEEE/ACM International Symposium on Microarchitecture |
| Publisher | IEEE Computer Society |
| Pages | 558-571 |
| Number of pages | 14 |
| ISBN (Electronic) | 9781450369381 |
| DOIs | |
| Publication status | Published - Oct 2019 |
| Event | 52nd Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 2019 - Columbus, United States Duration: 12 Oct 2019 → 16 Oct 2019 |
Publication series
| Name | Proceedings of the Annual International Symposium on Microarchitecture, MICRO |
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| ISSN (Print) | 1072-4451 |
Conference
| Conference | 52nd Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 2019 |
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| Country/Territory | United States |
| City | Columbus |
| Period | 12/10/19 → 16/10/19 |
Funding
This work was partially supported by ONR N00014–16–1–2263, ONR N00014–17–1–2788, ONR N00014–15–1–2173, DARPA HR0011–18–C–0017, and a gift from Bloomberg. The authors thank Prof. Mingoo Seok for access to SRAM timing measurement tools. Any opinions, findings, conclusions and recommendations expressed in this material are those of the authors and do not necessarily reflect the views of the US government or commercial entities. Simha Sethumadhavan has a significant financial interest in Chip Scan Inc.
Keywords
- Caches
- Memory blacklisting
- Memory safety