Readout Firmware of the Vertex Locator for LHCb Run 3 and beyond

Karol Hennessy, Antonio Fernandez Prieto, Pablo Vazquez Regueiro, Jan Buytaert, Martin Van Beuzekom, Edgar Lemos Cid, Lars Eklund, Kristof De Bruyn, Sneha Naik, Manuel Schiller, Donal Murray, Alexander Leflat, Giovanni Bassi, Giovanni Punzi, Federico Lazzari, Michael J. Morello, Oscar Boente Garcia, Abraham Gallas Torreira, Beatriz Garcia Plana, Themis BowcockFrancesco Dettori, Karlis Dreimanis, Vinicius Franco Lima, David Hutchcroft, Kurt Rinnert, Tara Shears, Oscar Augusto, Victor Coco, Paula Collins, Tim Evans, Massi Ferro-Luzzi, Heinrich Schindler, Kazu Akiba, Elena Dall' Occo, Cristina Sanchez Graz, Wouter Hulsbergen, Daniel Hynds, Igor Kostiuk, Marcel Merk, Aleksandra Snoch, Dana Seman Bobulska, Silvia Borghi, Stefano De Capua, Deepanwita Dutta, Marco Gersabeck, Chris Parkes, Peter Svihra, Mark Williams, Galina Bogdanova, Vladimir Volkov, Pawel Kopciewicz, Maciej Majewski, Agnieszka Oblakowska-Mucha, Bartlomej Rachwal, Tomasz Szumlak, Lucas Meyer Garcia, Franciole Marinho, Larissa Helena Mendes, Irina Nasteva, Juan Otalora, Gabriel Rodrigues, Jaap Velthuis, Pawel Jalocha, Malcolm John, Nathan Jurik, Luke Scantlebury-Smead, John Back, Tim Gershon, Tom Latham, Andrew Morris

Research output: Contribution to JournalArticleAcademicpeer-review

Abstract

The new LHCb Vertex Locator (VELO) for LHCb, comprising a new pixel detector and readout electronics, will be installed in 2021 for data taking in Run 3 at the LHC. The electronics centers around the 'VeloPix' ASIC at the front-end operating in a trigger-less readout at 40MHz. A custom serializer, called gigabit wireline transmitter (GWT), and associated custom protocol have been designed for the VeloPix. The GWT data are sent from the serializers of the VeloPix at a line rate of 5.12 Gb/s, reaching a total data rate of 2-3 Tb/s for the full VELO detector. Data are sent over 300-m optic-fiber links to the control and readout electronics cards for deserialization and processing in Intel Arria 10 FPGAs. Because of the VeloPix trigger-less design, latency variances up to 12 $\mu \text{s}$ can occur between adjacent datagrams. It is therefore essential to buffer and synchronize the data in firmware prior to onward propagation or suffer a huge CPU-processing penalty. This article will describe the architecture of the readout firmware in detail with focus given to the resynchronization mechanism and techniques for cauterization. Issues found during readout commissioning, and scaling resource utilization, along with the their solutions, will be illustrated. The latest results of the firmware data-processing chain can be presented as well as the verification procedures employed in simulation. Challenges for the next generation of the detector will also be presented with ideas for a readout processing solution.
Original languageEnglish
Pages (from-to)2472-2479
JournalIEEE Transactions on Nuclear Science
Volume68
Issue number10
DOIs
Publication statusPublished - 1 Oct 2021
Externally publishedYes

Funding

This work was supported in part by CERN and the National Agencies: CAPES, CNPq, FAPERJ, and FINEP (Brazil); in part by INFN (Italy); in part by NWO (Netherlands); in part by MEiN and NCN (Poland) under Grant UMO-2018/31/B/ST2/03998; in part by MSHE (Russia); in part by MICINN (Spain); and in part by STFC (U.K.).

FundersFunder number
MEiN
MSHE
CERN
Science and Technology Facilities Council
Coordenação de Aperfeiçoamento de Pessoal de Nível Superior
Nederlandse Organisatie voor Wetenschappelijk Onderzoek
Conselho Nacional de Desenvolvimento Científico e Tecnológico
Instituto Nazionale di Fisica Nucleare
Narodowe Centrum NaukiUMO-2018/31/B/ST2/03998
Narodowe Centrum Nauki
Fundação Carlos Chagas Filho de Amparo à Pesquisa do Estado do Rio de Janeiro
Financiadora de Estudos e Projetos
Ministerio de Ciencia e Innovación

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