Suppressing the Oblivious RAM timing channel while making information leakage and program efficiency trade-offs

C.W. Fletchery; L. Ren; X. Yu; M. Van Dijk; O. Khan; S. Devadas

doi:10.1109/HPCA.2014.6835932

Suppressing the Oblivious RAM timing channel while making information leakage and program efficiency trade-offs

C.W. Fletchery, L. Ren, X. Yu, M. Van Dijk, O. Khan, S. Devadas

Research output: Chapter in Book / Report / Conference proceeding › Conference contribution › Academic › peer-review

Abstract

Oblivious RAM (ORAM) is an established cryptographic technique to hide a program's address pattern to an untrusted storage system. More recently, ORAM schemes have been proposed to replace conventional memory controllers in secure processor settings to protect against information leakage in external memory and the processor I/O bus. © 2014 IEEE.

Original language	English
Title of host publication	20th IEEE International Symposium on High Performance Computer Architecture, HPCA 2014
Publisher	IEEE Computer Society
Pages	213-224
ISBN (Print)	9781479930975
DOIs	https://doi.org/10.1109/HPCA.2014.6835932
Publication status	Published - 2014
Externally published	Yes
Event	20th IEEE International Symposium on High Performance Computer Architecture, HPCA 2014 - , United States Duration: 15 Feb 2014 → 19 Feb 2014

Publication series

Name	Proceedings - International Symposium on High-Performance Computer Architecture
ISSN (Print)	1530-0897

Conference

Conference	20th IEEE International Symposium on High Performance Computer Architecture, HPCA 2014
Country/Territory	United States
Period	15/02/14 → 19/02/14

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

Access to Document

10.1109/HPCA.2014.6835932

Persistent URL (handle)

Copy link address

Cite this

Fletchery, C. W., Ren, L., Yu, X., Van Dijk, M., Khan, O., & Devadas, S. (2014). Suppressing the Oblivious RAM timing channel while making information leakage and program efficiency trade-offs. In 20th IEEE International Symposium on High Performance Computer Architecture, HPCA 2014 (pp. 213-224). (Proceedings - International Symposium on High-Performance Computer Architecture). IEEE Computer Society. https://doi.org/10.1109/HPCA.2014.6835932

@inproceedings{b7016bb007924dda8fb131bbc571541b,

title = "Suppressing the Oblivious RAM timing channel while making information leakage and program efficiency trade-offs",

abstract = "Oblivious RAM (ORAM) is an established cryptographic technique to hide a program's address pattern to an untrusted storage system. More recently, ORAM schemes have been proposed to replace conventional memory controllers in secure processor settings to protect against information leakage in external memory and the processor I/O bus. {\textcopyright} 2014 IEEE.",

author = "C.W. Fletchery and L. Ren and X. Yu and {Van Dijk}, M. and O. Khan and S. Devadas",

year = "2014",

doi = "10.1109/HPCA.2014.6835932",

language = "English",

isbn = "9781479930975",

series = "Proceedings - International Symposium on High-Performance Computer Architecture",

publisher = "IEEE Computer Society",

pages = "213--224",

booktitle = "20th IEEE International Symposium on High Performance Computer Architecture, HPCA 2014",

note = "20th IEEE International Symposium on High Performance Computer Architecture, HPCA 2014 ; Conference date: 15-02-2014 Through 19-02-2014",

}

Fletchery, CW, Ren, L, Yu, X, Van Dijk, M, Khan, O & Devadas, S 2014, Suppressing the Oblivious RAM timing channel while making information leakage and program efficiency trade-offs. in 20th IEEE International Symposium on High Performance Computer Architecture, HPCA 2014. Proceedings - International Symposium on High-Performance Computer Architecture, IEEE Computer Society, pp. 213-224, 20th IEEE International Symposium on High Performance Computer Architecture, HPCA 2014, United States, 15/02/14. https://doi.org/10.1109/HPCA.2014.6835932

Suppressing the Oblivious RAM timing channel while making information leakage and program efficiency trade-offs. / Fletchery, C.W.; Ren, L.; Yu, X. et al.
20th IEEE International Symposium on High Performance Computer Architecture, HPCA 2014. IEEE Computer Society, 2014. p. 213-224 (Proceedings - International Symposium on High-Performance Computer Architecture).

Research output: Chapter in Book / Report / Conference proceeding › Conference contribution › Academic › peer-review

TY - GEN

T1 - Suppressing the Oblivious RAM timing channel while making information leakage and program efficiency trade-offs

AU - Fletchery, C.W.

AU - Ren, L.

AU - Yu, X.

AU - Van Dijk, M.

AU - Khan, O.

AU - Devadas, S.

PY - 2014

Y1 - 2014

N2 - Oblivious RAM (ORAM) is an established cryptographic technique to hide a program's address pattern to an untrusted storage system. More recently, ORAM schemes have been proposed to replace conventional memory controllers in secure processor settings to protect against information leakage in external memory and the processor I/O bus. © 2014 IEEE.

AB - Oblivious RAM (ORAM) is an established cryptographic technique to hide a program's address pattern to an untrusted storage system. More recently, ORAM schemes have been proposed to replace conventional memory controllers in secure processor settings to protect against information leakage in external memory and the processor I/O bus. © 2014 IEEE.

UR - http://www.scopus.com/inward/record.url?scp=84904012684&partnerID=8YFLogxK

U2 - 10.1109/HPCA.2014.6835932

DO - 10.1109/HPCA.2014.6835932

M3 - Conference contribution

SN - 9781479930975

T3 - Proceedings - International Symposium on High-Performance Computer Architecture

SP - 213

EP - 224

BT - 20th IEEE International Symposium on High Performance Computer Architecture, HPCA 2014

PB - IEEE Computer Society

T2 - 20th IEEE International Symposium on High Performance Computer Architecture, HPCA 2014

Y2 - 15 February 2014 through 19 February 2014

ER -

Fletchery CW, Ren L, Yu X, Van Dijk M, Khan O, Devadas S. Suppressing the Oblivious RAM timing channel while making information leakage and program efficiency trade-offs. In 20th IEEE International Symposium on High Performance Computer Architecture, HPCA 2014. IEEE Computer Society. 2014. p. 213-224. (Proceedings - International Symposium on High-Performance Computer Architecture). doi: 10.1109/HPCA.2014.6835932

Suppressing the Oblivious RAM timing channel while making information leakage and program efficiency trade-offs

Abstract

Publication series

Conference

UN SDGs

Access to Document

Persistent URL (handle)

Other files and links

Fingerprint

Cite this