System-Level Timing Performance Estimation Based on a Unifying HW/SW Performance Metric

Vittoriano Muttillo; Vincenzo Stoico; Giacomo Valente; Marco Santic; Luigi Pomante; Daniele Frigioni

doi:10.4230/OASIcs.PARMA-DITAM.2025.3

System-Level Timing Performance Estimation Based on a Unifying HW/SW Performance Metric

Vittoriano Muttillo^*, Vincenzo Stoico^*, Giacomo Valente^*, Marco Santic^*, Luigi Pomante^*, Daniele Frigioni^*

^*Corresponding author for this work

Research output: Chapter in Book / Report / Conference proceeding › Conference contribution › Academic › peer-review

Abstract

The rapidly increasing complexity of embedded systems and the critical impact of non-functional requirements demand the adoption of an appropriate system-level HW/SW co-design methodology. This methodology tries to satisfy all design requirements by simultaneously considering several alternative HW/SW implementations. In this context, early performance estimation approaches are crucial in reducing the design space, thereby minimizing design time and cost. To address the challenge of system-level performance estimation, this work presents and formalizes a novel approach based on a unifying HW/SW performance metric for early execution time estimation. The proposed approach estimates the execution time of a C function when executed by different HW/SW processor technologies. The approach is validated through an extensive experimental study, demonstrating its effectiveness and efficiency in terms of estimation error (i.e., lower than 10%) and estimation time (close to zero) when compared to existing methods in the literature.

Original language	English
Title of host publication	16th Workshop on Parallel Programming and Run-Time Management Techniques for Many-Core Architectures and 14th Workshop on Design Tools and Architectures for Multicore Embedded Computing Platforms, PARMA-DITAM 2025
Editors	Daniele Cattaneo, Maria Fazio, Leonidas Kosmidis, Gabriele Morabito
Publisher	Schloss Dagstuhl- Leibniz-Zentrum fur Informatik GmbH, Dagstuhl Publishing
Pages	1-14
Number of pages	14
ISBN (Electronic)	9783959773638
DOIs	https://doi.org/10.4230/OASIcs.PARMA-DITAM.2025.3
Publication status	Published - 2025
Event	16th Workshop on Parallel Programming and Run-Time Management Techniques for Many-Core Architectures and 14th Workshop on Design Tools and Architectures for Multicore Embedded Computing Platforms, PARMA-DITAM 2025 - Barcelona, Spain Duration: 22 Jan 2025 → …

Publication series

Name	OpenAccess Series in Informatics
Volume	127
ISSN (Print)	2190-6807

Conference

Conference	16th Workshop on Parallel Programming and Run-Time Management Techniques for Many-Core Architectures and 14th Workshop on Design Tools and Architectures for Multicore Embedded Computing Platforms, PARMA-DITAM 2025
Country/Territory	Spain
City	Barcelona
Period	22/01/25 → …

Bibliographical note

Publisher Copyright:
© Vittoriano Muttillo, Vincenzo Stoico, Giacomo Valente, Marco Santic, Luigi Pomante, and Daniele Frigioni.

Keywords

embedded systems
hw/sw co-design
lasso
machine learning
performance estimation

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10.4230/OASIcs.PARMA-DITAM.2025.3Licence: CC BY

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Muttillo, V., Stoico, V., Valente, G., Santic, M., Pomante, L., & Frigioni, D. (2025). System-Level Timing Performance Estimation Based on a Unifying HW/SW Performance Metric. In D. Cattaneo, M. Fazio, L. Kosmidis, & G. Morabito (Eds.), 16th Workshop on Parallel Programming and Run-Time Management Techniques for Many-Core Architectures and 14th Workshop on Design Tools and Architectures for Multicore Embedded Computing Platforms, PARMA-DITAM 2025 (pp. 1-14). Article 3 (OpenAccess Series in Informatics; Vol. 127). Schloss Dagstuhl- Leibniz-Zentrum fur Informatik GmbH, Dagstuhl Publishing. https://doi.org/10.4230/OASIcs.PARMA-DITAM.2025.3

Muttillo, Vittoriano ; Stoico, Vincenzo ; Valente, Giacomo et al. / System-Level Timing Performance Estimation Based on a Unifying HW/SW Performance Metric. 16th Workshop on Parallel Programming and Run-Time Management Techniques for Many-Core Architectures and 14th Workshop on Design Tools and Architectures for Multicore Embedded Computing Platforms, PARMA-DITAM 2025. editor / Daniele Cattaneo ; Maria Fazio ; Leonidas Kosmidis ; Gabriele Morabito. Schloss Dagstuhl- Leibniz-Zentrum fur Informatik GmbH, Dagstuhl Publishing, 2025. pp. 1-14 (OpenAccess Series in Informatics).

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title = "System-Level Timing Performance Estimation Based on a Unifying HW/SW Performance Metric",

abstract = "The rapidly increasing complexity of embedded systems and the critical impact of non-functional requirements demand the adoption of an appropriate system-level HW/SW co-design methodology. This methodology tries to satisfy all design requirements by simultaneously considering several alternative HW/SW implementations. In this context, early performance estimation approaches are crucial in reducing the design space, thereby minimizing design time and cost. To address the challenge of system-level performance estimation, this work presents and formalizes a novel approach based on a unifying HW/SW performance metric for early execution time estimation. The proposed approach estimates the execution time of a C function when executed by different HW/SW processor technologies. The approach is validated through an extensive experimental study, demonstrating its effectiveness and efficiency in terms of estimation error (i.e., lower than 10%) and estimation time (close to zero) when compared to existing methods in the literature.",

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author = "Vittoriano Muttillo and Vincenzo Stoico and Giacomo Valente and Marco Santic and Luigi Pomante and Daniele Frigioni",

note = "Publisher Copyright: {\textcopyright} Vittoriano Muttillo, Vincenzo Stoico, Giacomo Valente, Marco Santic, Luigi Pomante, and Daniele Frigioni.; 16th Workshop on Parallel Programming and Run-Time Management Techniques for Many-Core Architectures and 14th Workshop on Design Tools and Architectures for Multicore Embedded Computing Platforms, PARMA-DITAM 2025 ; Conference date: 22-01-2025",

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Muttillo, V, Stoico, V, Valente, G, Santic, M, Pomante, L & Frigioni, D 2025, System-Level Timing Performance Estimation Based on a Unifying HW/SW Performance Metric. in D Cattaneo, M Fazio, L Kosmidis & G Morabito (eds), 16th Workshop on Parallel Programming and Run-Time Management Techniques for Many-Core Architectures and 14th Workshop on Design Tools and Architectures for Multicore Embedded Computing Platforms, PARMA-DITAM 2025., 3, OpenAccess Series in Informatics, vol. 127, Schloss Dagstuhl- Leibniz-Zentrum fur Informatik GmbH, Dagstuhl Publishing, pp. 1-14, 16th Workshop on Parallel Programming and Run-Time Management Techniques for Many-Core Architectures and 14th Workshop on Design Tools and Architectures for Multicore Embedded Computing Platforms, PARMA-DITAM 2025, Barcelona, Spain, 22/01/25. https://doi.org/10.4230/OASIcs.PARMA-DITAM.2025.3

System-Level Timing Performance Estimation Based on a Unifying HW/SW Performance Metric. / Muttillo, Vittoriano; Stoico, Vincenzo; Valente, Giacomo et al.
16th Workshop on Parallel Programming and Run-Time Management Techniques for Many-Core Architectures and 14th Workshop on Design Tools and Architectures for Multicore Embedded Computing Platforms, PARMA-DITAM 2025. ed. / Daniele Cattaneo; Maria Fazio; Leonidas Kosmidis; Gabriele Morabito. Schloss Dagstuhl- Leibniz-Zentrum fur Informatik GmbH, Dagstuhl Publishing, 2025. p. 1-14 3 (OpenAccess Series in Informatics; Vol. 127).

Research output: Chapter in Book / Report / Conference proceeding › Conference contribution › Academic › peer-review

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AU - Muttillo, Vittoriano

AU - Stoico, Vincenzo

AU - Valente, Giacomo

AU - Santic, Marco

AU - Pomante, Luigi

AU - Frigioni, Daniele

N1 - Publisher Copyright: © Vittoriano Muttillo, Vincenzo Stoico, Giacomo Valente, Marco Santic, Luigi Pomante, and Daniele Frigioni.

PY - 2025

Y1 - 2025

N2 - The rapidly increasing complexity of embedded systems and the critical impact of non-functional requirements demand the adoption of an appropriate system-level HW/SW co-design methodology. This methodology tries to satisfy all design requirements by simultaneously considering several alternative HW/SW implementations. In this context, early performance estimation approaches are crucial in reducing the design space, thereby minimizing design time and cost. To address the challenge of system-level performance estimation, this work presents and formalizes a novel approach based on a unifying HW/SW performance metric for early execution time estimation. The proposed approach estimates the execution time of a C function when executed by different HW/SW processor technologies. The approach is validated through an extensive experimental study, demonstrating its effectiveness and efficiency in terms of estimation error (i.e., lower than 10%) and estimation time (close to zero) when compared to existing methods in the literature.

AB - The rapidly increasing complexity of embedded systems and the critical impact of non-functional requirements demand the adoption of an appropriate system-level HW/SW co-design methodology. This methodology tries to satisfy all design requirements by simultaneously considering several alternative HW/SW implementations. In this context, early performance estimation approaches are crucial in reducing the design space, thereby minimizing design time and cost. To address the challenge of system-level performance estimation, this work presents and formalizes a novel approach based on a unifying HW/SW performance metric for early execution time estimation. The proposed approach estimates the execution time of a C function when executed by different HW/SW processor technologies. The approach is validated through an extensive experimental study, demonstrating its effectiveness and efficiency in terms of estimation error (i.e., lower than 10%) and estimation time (close to zero) when compared to existing methods in the literature.

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KW - hw/sw co-design

KW - lasso

KW - machine learning

KW - performance estimation

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Muttillo V, Stoico V, Valente G, Santic M, Pomante L, Frigioni D. System-Level Timing Performance Estimation Based on a Unifying HW/SW Performance Metric. In Cattaneo D, Fazio M, Kosmidis L, Morabito G, editors, 16th Workshop on Parallel Programming and Run-Time Management Techniques for Many-Core Architectures and 14th Workshop on Design Tools and Architectures for Multicore Embedded Computing Platforms, PARMA-DITAM 2025. Schloss Dagstuhl- Leibniz-Zentrum fur Informatik GmbH, Dagstuhl Publishing. 2025. p. 1-14. 3. (OpenAccess Series in Informatics). Epub 2025 Feb 27. doi: 10.4230/OASIcs.PARMA-DITAM.2025.3

System-Level Timing Performance Estimation Based on a Unifying HW/SW Performance Metric

Abstract

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Bibliographical note

Keywords

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