Tardis: A Fault-Tolerant Design for Network Control Planes

Zhenyu Zhou; Theophilus A. Benson; Marco Canini; Balakrishnan Chandrasekaran

doi:10.1145/3482898.3483355

Tardis: A Fault-Tolerant Design for Network Control Planes

Zhenyu Zhou, Theophilus A. Benson, Marco Canini, Balakrishnan Chandrasekaran

Research output: Chapter in Book / Report / Conference proceeding › Conference contribution › Academic › peer-review

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Abstract

Guaranteeing high availability of networks virtually hinges on the ability to handle and recover from bugs and failures. Yet, despite the advances in verification, testing, and debugging, production networks remain susceptible to large-scale failures - - often due to deterministic bugs. This paper explores the use of input transformations as a viable method for recovering from such deterministic bugs. In particular, we introduce an online system, Tardis, for overcoming deterministic faults by using a blend of program analysis and runtime program data to systematically determine the fault-triggering input events and using domain-specific models to automatically generate transformations of the fault-triggering inputs that are both safe and semantically equivalent. We evaluated Tardison several production network control plane applications (CPAs), including six SDN CPAs and several popular BGP CPAs using 71 realistic bugs. We observe that Tardisimproves recovery time by 7.44%, introduces a 25% CPU and 0.5% memory overhead, and recovers from 77.26% of the injected realistic and representative bugs, more than twice that of existing solutions.

Original language	English
Title of host publication	SOSR 2021
Subtitle of host publication	Proceedings of the 2021 ACM SIGCOMM Symposium on SDN Research (SOSR)
Publisher	Association for Computing Machinery, Inc
Pages	108-121
Number of pages	14
ISBN (Electronic)	9781450390842
DOIs	https://doi.org/10.1145/3482898.3483355
Publication status	Published - Oct 2021
Event	2021 ACM SIGCOMM Symposium on SDN Research, SOSR 2021 - Virtual, Online, United States Duration: 20 Sept 2021 → 21 Sept 2021

Conference

Conference	2021 ACM SIGCOMM Symposium on SDN Research, SOSR 2021
Country/Territory	United States
City	Virtual, Online
Period	20/09/21 → 21/09/21

Bibliographical note

Funding Information:
We thank the anonymous reviewers and our shepherd, Ryan Beckett, for their insightful comments. We also thank Ayush Bhardwaj for helping us with designing our experiments. This work was supported by NSF award CNS-1749785.

Publisher Copyright:
© 2021 ACM.

Funding

We thank the anonymous reviewers and our shepherd, Ryan Beckett, for their insightful comments. We also thank Ayush Bhardwaj for helping us with designing our experiments. This work was supported by NSF award CNS-1749785.

Keywords

control plane
failure recovery
Software Defined Networks
transformation

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10.1145/3482898.3483355

Tardis_A FaultTolerant Design for Network Control PlanesFinal published version, 1.18 MBLicence: Article 25fa Dutch Copyright Act

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Cite this

@inproceedings{111d50e2d4f54773a8573de1e2c85d03,

title = "Tardis: A Fault-Tolerant Design for Network Control Planes",

abstract = "Guaranteeing high availability of networks virtually hinges on the ability to handle and recover from bugs and failures. Yet, despite the advances in verification, testing, and debugging, production networks remain susceptible to large-scale failures - - often due to deterministic bugs. This paper explores the use of input transformations as a viable method for recovering from such deterministic bugs. In particular, we introduce an online system, Tardis, for overcoming deterministic faults by using a blend of program analysis and runtime program data to systematically determine the fault-triggering input events and using domain-specific models to automatically generate transformations of the fault-triggering inputs that are both safe and semantically equivalent. We evaluated Tardison several production network control plane applications (CPAs), including six SDN CPAs and several popular BGP CPAs using 71 realistic bugs. We observe that Tardisimproves recovery time by 7.44\%, introduces a 25\% CPU and 0.5\% memory overhead, and recovers from 77.26\% of the injected realistic and representative bugs, more than twice that of existing solutions.",

keywords = "control plane, failure recovery, Software Defined Networks, transformation",

author = "Zhenyu Zhou and Benson, \{Theophilus A.\} and Marco Canini and Balakrishnan Chandrasekaran",

note = "Funding Information: We thank the anonymous reviewers and our shepherd, Ryan Beckett, for their insightful comments. We also thank Ayush Bhardwaj for helping us with designing our experiments. This work was supported by NSF award CNS-1749785. Publisher Copyright: {\textcopyright} 2021 ACM.; 2021 ACM SIGCOMM Symposium on SDN Research, SOSR 2021 ; Conference date: 20-09-2021 Through 21-09-2021",

year = "2021",

month = oct,

doi = "10.1145/3482898.3483355",

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Zhou, Z, Benson, TA, Canini, M & Chandrasekaran, B 2021, Tardis: A Fault-Tolerant Design for Network Control Planes. in SOSR 2021: Proceedings of the 2021 ACM SIGCOMM Symposium on SDN Research (SOSR). Association for Computing Machinery, Inc, pp. 108-121, 2021 ACM SIGCOMM Symposium on SDN Research, SOSR 2021, Virtual, Online, United States, 20/09/21. https://doi.org/10.1145/3482898.3483355

Tardis: A Fault-Tolerant Design for Network Control Planes. / Zhou, Zhenyu; Benson, Theophilus A.; Canini, Marco et al.
SOSR 2021: Proceedings of the 2021 ACM SIGCOMM Symposium on SDN Research (SOSR). Association for Computing Machinery, Inc, 2021. p. 108-121.

Research output: Chapter in Book / Report / Conference proceeding › Conference contribution › Academic › peer-review

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N1 - Funding Information: We thank the anonymous reviewers and our shepherd, Ryan Beckett, for their insightful comments. We also thank Ayush Bhardwaj for helping us with designing our experiments. This work was supported by NSF award CNS-1749785. Publisher Copyright: © 2021 ACM.

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N2 - Guaranteeing high availability of networks virtually hinges on the ability to handle and recover from bugs and failures. Yet, despite the advances in verification, testing, and debugging, production networks remain susceptible to large-scale failures - - often due to deterministic bugs. This paper explores the use of input transformations as a viable method for recovering from such deterministic bugs. In particular, we introduce an online system, Tardis, for overcoming deterministic faults by using a blend of program analysis and runtime program data to systematically determine the fault-triggering input events and using domain-specific models to automatically generate transformations of the fault-triggering inputs that are both safe and semantically equivalent. We evaluated Tardison several production network control plane applications (CPAs), including six SDN CPAs and several popular BGP CPAs using 71 realistic bugs. We observe that Tardisimproves recovery time by 7.44%, introduces a 25% CPU and 0.5% memory overhead, and recovers from 77.26% of the injected realistic and representative bugs, more than twice that of existing solutions.

AB - Guaranteeing high availability of networks virtually hinges on the ability to handle and recover from bugs and failures. Yet, despite the advances in verification, testing, and debugging, production networks remain susceptible to large-scale failures - - often due to deterministic bugs. This paper explores the use of input transformations as a viable method for recovering from such deterministic bugs. In particular, we introduce an online system, Tardis, for overcoming deterministic faults by using a blend of program analysis and runtime program data to systematically determine the fault-triggering input events and using domain-specific models to automatically generate transformations of the fault-triggering inputs that are both safe and semantically equivalent. We evaluated Tardison several production network control plane applications (CPAs), including six SDN CPAs and several popular BGP CPAs using 71 realistic bugs. We observe that Tardisimproves recovery time by 7.44%, introduces a 25% CPU and 0.5% memory overhead, and recovers from 77.26% of the injected realistic and representative bugs, more than twice that of existing solutions.

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Tardis: A Fault-Tolerant Design for Network Control Planes

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Keywords

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