TY - GEN
T1 - Using chip multithreading to speed up scenario-based design space exploration
T2 - 2014 4th Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools, RAPIDO 2014 - In Conjunction with the 9th Intl. Conference on High-Performance and Embedded Architectures and Compilers, HiPEAC 2014
AU - Van Stralen, Peter
AU - Pimentel, Andy D.
PY - 2014/1/1
Y1 - 2014/1/1
N2 - Early design space exploration (DSE) is a key element of systemlevel design of complex embedded systems, helping designers to make design decisions during the early design phases. For early DSE, where the design space is vast, it is crucial that the exploration process is as efficient as possible. In this paper, we describe the implementation of our scenario-based DSE framework on a Chip Multithreading platform, namely the SPARC T3-4 server, and study its performance behavior in detail.
AB - Early design space exploration (DSE) is a key element of systemlevel design of complex embedded systems, helping designers to make design decisions during the early design phases. For early DSE, where the design space is vast, it is crucial that the exploration process is as efficient as possible. In this paper, we describe the implementation of our scenario-based DSE framework on a Chip Multithreading platform, namely the SPARC T3-4 server, and study its performance behavior in detail.
KW - Chip multithreading
KW - Implementation study
KW - Scenario-based design space exploration
UR - http://www.scopus.com/inward/record.url?scp=84901059959&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=84901059959&partnerID=8YFLogxK
M3 - Conference contribution
AN - SCOPUS:84901059959
SN - 9781450324717
T3 - ACM International Conference Proceeding Series
BT - RAPIDO 2014 - Proceedings of the 2014 Workshop on Rapid Simulation and Performance Evaluation
PB - Association for Computing Machinery
Y2 - 22 January 2014 through 22 January 2014
ER -